//DHEERAJ KUMAR BISWAS

//`include "slaveBlock.v"

module slaveSel(clk,
				resetn,
				PADDR,
				PPROT,
                PSEL,
				PENABLE,
				PWRITE,
				PWDATA,
			    PSTRB,
			    PREADY,
			    PRDATA,
			    PSLVERR
			    /*CMD*/);
	
	//parameter declarations
	parameter DATA_WIDTH	 = 32;
	parameter MEMORY_WIDTH	 = 1024;
	parameter WR1_RD0	 	 = 1;
    parameter SLV_SEL 	 	 = 2;
	parameter ADDR_WIDTH   	 = 10; //log2(MEMORY_WIDTH);
	parameter STRB_WIDTH	 = 4; //log2(DATA_WIDTH-8);
	//parameter CMD_LENGTH = DATA_WIDTH + ADDR_WIDTH + WR1_RD0 + SLV_SEL;

	input						clk;
	input						resetn;
	input	[ADDR_WIDTH-1:0]	PADDR;
	input						PPROT;
  	input	[SLV_SEL-1:0]		PSEL;
	input						PENABLE;
	input						PWRITE;
	input	[DATA_WIDTH-1:0]	PWDATA;
	input	[STRB_WIDTH-1:0]  	PSTRB;
	//input	[CMD_LENGTH-1:0]	CMD;
    output 						PREADY;
	output  [DATA_WIDTH-1:0]	PRDATA;
	output 						PSLVERR;
	
    //internal signal declaration
  wire [3:0] SS_PREADY, SS_PSLVERR;
  reg WPREADY, WPSLVERR;
  wire [DATA_WIDTH-1:0] SS_PRDATA0, SS_PRDATA1, SS_PRDATA2, SS_PRDATA3;
  reg [DATA_WIDTH-1:0] WPRDATA;
  integer n;
 
  slaveBlock S0(.clk		(clk),
                .resetn		(resetn),
                .PADDR		(PADDR),
                .PPROT		(PPROT),
                .PSEL		(!(PSEL[1])&& !(PSEL[0])),
                .PENABLE	(PENABLE &&(!(PSEL[1])&& !(PSEL[0]))),
                .PWRITE		(PWRITE),
                .PWDATA		(PWDATA),
                .PSTRB		(PSTRB),
                .PREADY		(SS_PREADY[0]),
                .PRDATA		(SS_PRDATA0),
                .PSLVERR 	(SS_PSLVERR[0]));

  slaveBlock S1(clk,
				resetn,
				PADDR,
				PPROT,
              	(!(PSEL[1]) && PSEL[0]),
              	PENABLE,
				PWRITE,
				PWDATA,
			    PSTRB,
              	SS_PREADY[1],
              	SS_PRDATA1,
              	SS_PSLVERR[1]);

  slaveBlock S2(clk,
				resetn,
				PADDR,
				PPROT,
              	(PSEL[1] && !(PSEL[0])),
              	PENABLE,
				PWRITE,
				PWDATA,
			    PSTRB,
              	SS_PREADY[2],
              	SS_PRDATA2,
              	SS_PSLVERR[2]);

  slaveBlock S3(clk,
				resetn,
				PADDR,
				PPROT,
              	(PSEL[1] && PSEL[0]),
              	PENABLE,
				PWRITE,
				PWDATA,
			    PSTRB,
              	SS_PREADY[3],
			    SS_PRDATA3,
              	SS_PSLVERR[3]);
  
    assign PREADY = (!(PSEL[1])&& !(PSEL[0]))?SS_PREADY[0]:(!(PSEL[1])&& (PSEL[0]))?SS_PREADY[1]:((PSEL[1])&& !(PSEL[0]))?SS_PREADY[2]:((PSEL[1])&& (PSEL[0]))?SS_PREADY[3]:0;
  
    assign PRDATA = (!(PSEL[1])&& !(PSEL[0]))?SS_PRDATA0:(!(PSEL[1])&& (PSEL[0]))?SS_PRDATA1:((PSEL[1])&& !(PSEL[0]))?SS_PRDATA2:((PSEL[1])&& (PSEL[0]))?SS_PRDATA3:0;
  
	assign PSLVERR = (!(PSEL[1])&& !(PSEL[0]))?SS_PSLVERR[0]:(!(PSEL[1])&& (PSEL[0]))?SS_PSLVERR[1]:((PSEL[1])&& !(PSEL[0]))?SS_PSLVERR[2]:((PSEL[1])&& (PSEL[0]))?SS_PSLVERR[3]:0;
    
endmodule
